High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware

This paper describes the principles of high level modeling of digital hardware circuits using the Extended Timing Diagrams (ETD) formalism which adds conditions, events, action expressions and particular constraints to traditional timing diagrams. Hierarchy and concurrency are integrated too such that a full top-down design becomes possible, enhancing in the same time the readability. While for simulation purposes, the implementation of the formalism generates behavioral VHDL (VHSIC Hardware Description Language) models, a dedicated high-level translator generates VHDL code for synthesis. Both the ETD formalism and its implementation are part of MODES, a more complex modeling expert system including complementary editors.